Dr. Anuja George
Assistant Professor
Department of Electronics and Communication Engineering
Mobile Number: +91 9048409677
Email: anujageorge@sjcetpalai.ac.in
Date of joining SJCET: 03/01/2012
Association with the institution: Regular
| Degree | Specialization | Institution | University | Year of Passing |
|---|---|---|---|---|
| B. Tech. | Electronics and Communication Engineering | SCMS School of Engineering and Technology, Ernakulam | Mahatma Gandhi University | 2009 |
| M. Tech. | VLSI and Embedded Systems | Rajagiri School of Engineering and Technology, Ernakulam. | Mahatma Gandhi University | 2011 |
| Ph. D | Design and Implementation of Hardware-Efficient VLSI Architectures for Image Processing | National Institute of Technology Calicut | National Institute of Technology Calicut | 2024 |
| Name of the College / Industry | Designation | Date of Joining | Date of Relieving |
|---|---|---|---|
| St. Joseph's College of Engineering & Technology, Palai | Assistant Professor | Jan 3, 2012 | till date |
| Particulars | Membership ID/No |
|---|---|
| ISTE | LM 90175 |
- George and EP Jayakumar, “Design and Implementation of Hardware-Efficient Noise-Level Estimation for Image Denoising with FrWF and Polynomial Regression-based Edge Detection,” IEEE Sensors J., 2025. (SCIE)
- George, EP Jayakumar, “Hardware‑efficient FrWF‑based architecture for joint image dehazing and denoising framework for visual sensors,” J. Real-Time Image Process., vol. 22, no. 1, pp. 14, Jan 2025, https://doi.org/10.1007/s11554-024-01568-9 (SCIE).
- George, EP Jayakumar, “Design and Implementation of Hardware-Efficient Architecture for Saturation-based Image Dehazing Algorithm,” J. Real-Time Image Process., vol. 20, no. 5, pp. 102, Oct. 2023, https://doi.org/10.1007/s11554-023-01356-x (SCIE).
- George and EP Jayakumar, “Hardware-Efficient DWT Architecture for Image Processing in Visual Sensors Networks,” IEEE Sensors J., vol. 23, no. 5, pp. 5382-5390, March 2023, doi: 10.1109/JSEN.2023.3235371(SCIE).
- George, A. Thomas, A. Abraham, J. Jose, and J. Joseph, “SAFE RIDE: An Integrated Bike Safety System with Crash Detection,” Proceedings of the 7th International Conference on Intelligent Sustainable Systems (ICISS-2025), Tirunelveli, India, pp. 157-164, 2025, ISBN: 979-8-3315-2242-1
- Abhisree B, Ann Maria Johney, Jose Abraham, Josil N D, Anuja George, Sreesh P R, “Smart Wearable Jacket for Assisted Outdoor Navigation of Visually Impaired,” Proceedings of KETCON, pp. 67, 16th-18th Feb 2024.
- Abhin Jin, Alan Thomas, Deepu C D, Rehan M Patani, Anuja George, “IOT Based Smart School Bus Monitoring and Security System,” Proceedings of KETCON, pp. 68, 16th-18th Feb 2024.
- S Devitha, A. George, “Design of Low Power High-Speed SAR ADC-A Review,” Proceedings of the 3rd International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, pp. 864-868, 2019, doi: 10.1109/ICCMC.2019.8819791, ISBN: 978-1-5386-7808-4
- Raj, A George, “FPGA Implementation of EEG Feature Extraction and Seizure Detection,” International Journal of Innovative Research in Science, Engineering and Technology, vol. 5, no. 9, pp. 1111-1117, Sept. 2016, DOI:10.15680/IJIRSET.2016.0509111
- George, S. Raj, “Speedy Convolution Using Reversible Vedic Multiplier,” International Journal of Scientific and Research Publications, vol. 6, no. 9, pp. 286-291, Sept. 2016, ISSN 2250-3153
- James, N R, A George, “Design and validation of SHA 384 IP core,” International Journal of Computer Science & Technology, vol. 5, no. 3, pp. 31-34, Sept. 2014, ISSN: 0976-8491 (Online)
- C.J, A. George, A. V, “A Novel IEEE 754 Standard Floating-Point Unit Comprising Fused Add-Subtract Unit,” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE), vol. 2, Special Issue 1, pp. 568-575, Dec. 2013, ISSN (Online): 2278 – 8875
- A George, “A Novel Design of Low Power, High-Speed SAMM and its FPGA Implementation,” International Journal of Computer Applications (IJCA), vol. 43, no.4, pp. 6-9, April 2012, DOI=10.5120/6089-8263
- A George, “A Novel Low Power Design of SRAM Cell And Its Performance Analysis,” International Journal of Computer Applications (IJCA), pp. 20-25, 2011.
- Attended a FDP on Unleashing the Potential of System-on-Chip and its Architecture organized by AICTE Training and Learning (ATAL) Academy during 15 th – 20 th Jan, 2024.
- Attended a Self-Sponsored Faculty Development Program on Chip Design (Chip2023) organized by NIT Calicut in collaboration with IBM during 3 rd – 7 th July, 2023.
- Attended a STTP on VLSI Architectures for Digital Signal Processing Systems (VADSPS-21) organized by NIT Calicut during 14 th – 18 th June, 2021.
- Attended a TEQIP-III Sponsored FDP on Research Trends in Multimedia and Multirate Signal Processing (RTMMSP 19) organized by NIT Calicut under twinning with Govt. Engineering College Bharatpur, Rajasthan during 24 th – 29 th June, 2019.
- Attended a ISTE STTP on CMOS, Mixed Signals & Radio Frequency VLSI Design organized by IIT Kharagpur during 30 th Jan – 4 th Feb, 2017.
- Attended a IETE Sponsored FDP on Embedded Design Using ARM and ARDUINO organized by Saintgits College of Engineering and Technology, Kottayam, during 18 th – 24 th Nov, 2015.
- Attended a FDP on Wireless Communication Networks organized by Adi Shankara Institute of Engineering and Technology during 24 th – 28 th Nov 2014.
- Attended a Two-week ISTE workshop on Signals & Systems organized by IIT Kharagpur during 2 nd – 12 th Jan, 2014.
- Attended a TEQIP Sponsored FDP on Advanced Digital Signal Processing TKM College of Engineering, Kollam, during 18 th – 22 nd Nov, 2013.
- Attended a AICTE Sponsored FDP on Electronics in Medical Diagnosis organized by Albertian Institute of Science and Technology (AISAT), Kalamassery, during 6 th – 17 th May, 2013.
- Participated and presented a research paper entitled SAFE RIDE: An Integrated Bike Safety System with Crash Detection at the 7th International Conference on Intelligent Sustainable Systems (ICISS-2025), Tirunelveli, India during 12-14 March 2025.
- Attended an International Symposium on Artificial Intelligence and Humanoid Technology organized by SJCET Palai in association with IISR, New Delhi during 2nd – 4th Jan, 2025.
- Attended a seminar on Advancements in Electronic Systems for Healthcare Applications organized by AICTE-VAANI during 29nd – 31th August, 2024.
- Participated and presented a paper entitled Design of Low Power High-Speed SAR ADC-A Review at the 3rd International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, during 27-29 March 2019.
- Participated in National conference on Innovative Engineering Technology organised by Christ University, Kengeri, Bangalore during 13th and 14th February 2015.
- Attended an Induction Training Programme on Teaching Excellence and Methodologies organized by ISTE Kerala section and ISTE GEC Trichur during 2 nd – 7 th July, 2012.
- Attended a Two-week ISTE workshop Introduction to Research Methodologies organized by IIT Bombay during 25 th June – 4 th July, 2012.
- Attended a National conference on Current advancements in Communication, Control and Instrumentation Engineering (NCCCIE-2012) organised by Federal Institute of Science and Technology during 17th and 18th May 2012.
- Twelve-week NPTEL-AICTE MOOC Course on ‘Digital Circuits’ organized by IIT Kharagpur, from July to Oct 2024.
- Reviewer of SCIE Journals – IEEE Transactions on Circuits and Systems for Video Technology, IEEE Transactions on Circuits and Systems II: Express Briefs, Analog Integrated Circuits and Signal Processing J., Signal, Image and Video J.
- Reviewer of 4th IEEE International Conference on Advances in Computing, Communication, Embedded and Secure Systems (ACCESS ’25), held during 11 to 13 June 2025, at Adi Shankara Institute of Engineering and Technology, Kalady, Kerala,
- Awarded “Elite” Certificate for completing the NPTEL MOOC course on Digital Circuits, Jul-Oct 2024.