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Anuja George

/Anuja George
Anuja George 2023-08-02T05:30:33+00:00

Prof. Anuja George

Assistant Professor
Department of Electronics and Communication Engineering
Mobile Number: +91 9048409677
Date of joining SJCET: 03/01/2012
Association with the institution: Regular

Sl.NoQualificationUniversityYear of passingSpecialization
1B.TechM.G University2009Electronics and Communication Engineering
2M.TechM.G University2011VLSI and Embedded Systems

Date of joining SJCET            : 03/03/2012

Status as on date of joining    : Assistant professor

Present status                   : Assistant professor

Sl. NoName of InstitutionType of MembershipMembership ID
Sl. NoName of Training/WorkshopYear & Date (Duration)Organizer
1Self-Sponsored Faculty Development Program On Chip Design (Chip2023)3-7 July 2023.NIT Calicut In Collaboration With IBM
2VLSI Architectures for Digital Signal Processing Systems (VADSPS-21)14-18 June, 2021NIT, Calicut
3Research Trends in Multimedia and Multirate Signal Processing (RTMMSP 18)June 4 - 9, 2018NIT, Calicut Under twinning with Govt. Engineering College Bharatpur
4CMOS, Mixed Signals & Radio Frequency VLSI Design30th Jan to 4th Feb,2017IIT,Kharagpur
5Embedded Design Using ARM and ARDUINO18/11/2015 to 24/11/2015Saintgits College of Engineering and Technology, Kottayam
6Wireless Communication Networks24th to 28th Nov 2014Adi Shankara Institute of Engineering and Technology
7Signals & Systems2nd  to 12th  Jan,  2014IIT,Kharagpur
8Advanced Digital Signal Processing18th to 22nd Nov, 2013TKM College of Engineering
9Electronics in Medical Diagnosis6th to 17th May 2013Albertian Institute of Science and Technology (AISAT), Kalamassery
10Introduction to research methodologies25th June to 4th July 2012IIT, Bombay
Sl.NoTitle of PaperName of journalPublisherYear, Volume & ISSN/ISBN No.
1Hardware-Efficient DWT Architecture for Image Processing in Visual Sensors NetworksIEEE Sensors Journal23(5), pp.5382-5390,March 2023
2FPGA Implementation of EEG Feature Extraction and Seizure DetectionInternational Journal of Innovative Research in Science, Engineering and TechnologyVol. 5, Issue 9, September 2016
3Speedy Convolution Using Reversible Vedic MultiplierInternational Journal of Scientific and Research PublicationsVolume 6, Issue 9, September 2016
4Design and validation of SHA 384 IP coreInternational Journal of Computer Science & TechnologyVOL5.3-1, September, 2014
5A   Novel IEEE 754 Standard Floating Point Unit Comprising Fused Add-Subtract UnitIJAREEIEVol. 2, Special Issue 1, December 2013
6A Novel Design of Low Power, High Speed SAMM and its FPGA ImplementationInternational Journal of Computer Applications (IJCA)Volume 43– No.4, April 2012
7A Novel Low Power Design of SRAM Cell And Its Performance AnalysisInternational Journal of Computer Applications (IJCA)2011