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Dr. George Tom Varghese

/Dr. George Tom Varghese
Dr. George Tom Varghese 2019-02-28T16:14:19+00:00

Dr. George Tom Varghese

Associate Professor
Department of Electronics and Communication Engineering
Mobile Number: +91 9437777895
Email: georgetomvarghese@sjcetpalai.ac.in
Date of joining SJCET : 17/06/2009
Association with the institution: Regular

Sl.No Qualification University Institution Year of passing Specialization Class/CGPA
1 B.Tech Cochin University of Science And Technology College of Engineering, Chengannur 2006 Electronics and Communication 72.98%
2 M.Tech NIT, Rourkela NIT, Rourkela 2009 VLSI Design & Embedded Systems 9.77

(First Rank )

3 Ph.D NIT, Rourkela NIT, Rourkela 2015 VLSI Design

Date of joining SJCET                                     : 17/06/2009

Status as on date of joining                             : Senior Lecturer

Present status                                                  :  Associate Professor

Sl. No Name of Institution Type of Membership Membership ID
1. ISTE LIFE MEMBER LM64510
 

Sl. No

 

Name of Training/Workshop Year & Date (Duration) Organizer
1. Digital System Design using Verilog HDL 19th April 2010- 30th April 2010 DOEACC CENTRE, CALICUT
Sl.No Title of Paper Name of journal Publisher Year, Volume & ISSN/ISBN No.
1. A Low Power Reconfigurable Encoder for Flash ADCs Procedia Technology ELSEVIER Volume 25, 2016, Pages 574-581
2. Low power Wallace tree encoder for Flash ADC IOP Science: Materials Science and Engineering, Materials Science and Engineering, Volume 396, Number 1
1 International Journals
2 National Journals
3 International conference
4 National Conference
4 Books/Book chapters/Monograph Published a book on “Pre-Commission Tests and Commissioning of Electrical Installations”
Sl. No.  Title of the Paper Name of the Conference Venue & Date
1. A high speed encoder for a 5GS/s 5 bit flash ADC ICCCNT July 2012
2. A high speed low power encoder for a 5 bit flash ADC ICGT December 2012
3. An ultra-low power encoder for 5 bit flash ADC ICEVENT January 2013
4. Negative body biased comparator Design for Biomedical applications IEEE international conference on intelligent computing, instrumentation and control technologies July 2017
5. Design of optimum power, delay efficient level shifter for biomedical applications IEEE international conference on intelligent computing, instrumentation and control technologies July 2017
6. Thermometer code to Binary code Converter for Flash ADC – A Review ICCPCCT April 2018
7. Design of Low Power and High Speed Modified Preamplifier based Comparator using 180 nm Technology ICCPCCT April 2018
 

Sl. No

 

Name of Conference Year & Duration Organizer
1. IEEE international conference on Next Generation Intelligent Systems (ICNGIS-2016) 1st September to 3rd September 2016. Rajiv Gandhi Institute of Technology, Kottayam

 

Sl. No Title/ Topic Year & Duration Organizer
1. Implementation of a novel flash ADC for UWB applications 14th to 15th July 2016. Two day national conference NACOSPACE-16  held in college of Engineering, Thalassery
2. Low power VLSI 6th September 2016 College of Engineering, Thalassery
3. Advancements in Digital System Design 28th October 2017 Rajiv Gandhi Institute of Technology, Pampady.
Sl. No Title/ Topic  Date & Duration Sponsors
1 ISTE STTP on CMOS, Mixed Signal and Radio frequency VLSI Design  30th January2017 – 4th February 2017 ISTE
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